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Altera_Forum
Honored Contributor
Honored ContributorNCO help...
Hi i'm trying to test a fixed point filter on a FPGA board, my filter has an input of 16 bit, but the maximum value it can take without saturation is 1023 which is 11 bits. so far the only signal i'v...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- No the blocks are in the right order, if you look at the link you see they are the same as the simulink model i posted. --- Quote End --- No that is not right. The link diagran puts H0 filter followed by down 2, your model puts rate transition then LOwPassFilter. Am I looking at the wrong link. Moreover it defies theory to put rate transition before decimating filter. For DSPBuilder you will choose blocks of decimator/interpolator and connect them. You choose your coeffs as well which might well be same as your or scaled for unity gain. The rate conversion is implied in the filter itself. Once done then you run DSPBuilder to generate code and testbench.
