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Altera_Forum's avatar
Altera_Forum
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14 years ago

NCO help...

Hi i'm trying to test a fixed point filter on a FPGA board, my filter has an input of 16 bit, but the maximum value it can take without saturation is 1023 which is 11 bits. so far the only signal i'v...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

No the blocks are in the right order, if you look at the link you see they are the same as the simulink model i posted. at this point i'm looking to do whatever it takes to make this work. i didn't know DSPbuilder was the industry standard. maybe i'll have better luck with that. how would i get this code into DSPbuilder, maybe then we'll be easier for us to be on the same page.

N = 99; [H0,H1,G0,G1] = firpr2chfb(N,.45);

% Analysis filters (decimators). Hlp = mfilt.firdecim(2,H0); Hhp = mfilt.firdecim(2,H1); % Synthesis filters (interpolators). Glp = mfilt.firinterp(2,G0); Ghp = mfilt.firinterp(2,G1);