Altera_Forum
Honored Contributor
14 years agominiproject
i got a title for miniproject like this,,
question-Develop a VHDL model for an accumulator that calculates the sum of a sequence of fixed-point numbers. Each input number is signed with 4 pre-binary-point and 12 post-binary-point bits. The accumulated sum has 8 pre-binary-point and 12 post-binary-point bits. A new number arrives at the input during a clock cycle when the data_en control input is 1. The accumulated sum is cleared to 0 when the reset control input is 1. Both control inputs are synchronous. and below is the code that i found.i've tried the code but it is not valid for more than 4-bits.is there anything wrong with the code?i also wanna know the meaning of "resize(data_in, sum'length)" in the code.is there any specific use or meaning of this code? library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; entity accumulator is port (clk,reset, data_en : in std_logic; data_in : in signed(3 downto 0); data_out : out signed(3 downto 0) ); end entity accumulator; architecture rtl of accumulator is signal sum, new_sum :signed(3 downto 0); begin new_sum <= sum + resize(data_in, sum'length); reg: process (clk) is begin if rising_edge(clk) then if reset = '1' then sum <= (others => '0'); elsif data_en = '1' then sum <= new_sum; end if; end if; end process reg; data_out <= sum; end architecture rtl; i'm glad if there's anybody wanna help asap before next week...