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Altera_Forum's avatar
Altera_Forum
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15 years ago

miniproject

i got a title for miniproject like this,, question-Develop a VHDL model for an accumulator that calculates the sum of a sequence of fixed-point numbers. Each input number is signed with 4 pre-bina...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

new_sum <= resize(sum + data_in, new_sum'length); -- something like that