Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorMinimum Pulse Width (dcfifo)
Hi,
I got many minimum pulse width timing violations (as the attached screenshot) related to the dcfifos in the design and don't know how to fix them. Could anyone point me to the right direction? Thanks, Hua9 Replies
Altera_ForumThank you, Netchuck.
Kaz has helped me getting to the bottom of this problem. You guys are awesome.- Altera_Forum
260MHz max - from CycloneIII faq:
embedded memory what type of embedded memory and memory features do cyclone iii fpgas have? Cyclone III FPGAs offer up to 4 Mbit of embedded memory. The embedded memory consists of columns of 9-Kbit (M9K) RAM blocks, each capable of data transfer rates up to 260 MHz. Each M9K RAM block can implement various types of memory, including true dual-port, simple dual-port, and single-port RAM, ROM, and first-in first-out (FIFO) buffers. Each block also includes extra parity bits for error control, mixed-width mode, and mixed-clock mode support. Please refer to the cyclone iii embedded memory page (http://www.altera.com/products/devices/cyclone3/overview/architecture/cy3-emb-memory.html) for more details. - Altera_Forum--- Quote Start --- More folks may be able to help if you attach your DCFIFO MegaWizard file along with the QSF file you are using. --- Quote End --- Thanks, please find the QSF file along with the generated megawizard files in the attachment.
- Altera_Forum--- Quote Start --- Among other things: You need to check that your clk speed is not too high for fifos, that fifo reset is synchronised to faster clk. It is all speculative. This error is very rare. You need to post as much info as possible. --- Quote End --- The wrclk is 320MHz and the rdclk is 32MHz. I am using Cyclone III. The reset is synchronized to the wrclk. Is it 320MHz too high for dcfifo in Cyclone III? How could I find out the maximum frequency dcfifo supports? Thanks, Hua
- Altera_Forum
More folks may be able to help if you attach your DCFIFO MegaWizard file along with the QSF file you are using.
- Altera_Forum
Among other things: You need to check that your clk speed is not too high for fifos, that fifo reset is synchronised to faster clk. It is all speculative. This error is very rare. You need to post as much info as possible.
- Altera_Forum--- Quote Start --- check your clks are not gated. If so register and make them global. Glitches on the clk signal cause this type of violation. --- Quote End --- Hi Kaz, Thank you for your reply. The clocks are all global. The attached are the clock report. Could anything else cause this? Hua
- Altera_Forum
check your clks are not gated. If so register and make them global. Glitches on the clk signal cause this type of violation.
- Altera_Forum
:confused: Not enough information?
