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Altera_Forum
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17 years ago

Minimum Pulse Width (dcfifo)

Hi, I got many minimum pulse width timing violations (as the attached screenshot) related to the dcfifos in the design and don't know how to fix them. Could anyone point me to the right directi...
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Altera_Forum
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17 years ago

260MHz max - from CycloneIII faq:

embedded memory

what type of embedded memory and memory features do cyclone iii fpgas have?

Cyclone III FPGAs offer up to 4 Mbit of embedded memory. The embedded memory consists of columns of 9-Kbit (M9K) RAM blocks, each capable of data transfer rates up to 260 MHz. Each M9K RAM block can implement various types of memory, including true dual-port, simple dual-port, and single-port RAM, ROM, and first-in first-out (FIFO) buffers. Each block also includes extra parity bits for error control, mixed-width mode, and mixed-clock mode support.

Please refer to the cyclone iii embedded memory page (http://www.altera.com/products/devices/cyclone3/overview/architecture/cy3-emb-memory.html) for more details.