Minimum Pulse Width (dcfifo)

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Among other things: You need to check that your clk speed is not too high for fifos, that fifo reset is synchronised to faster clk. It is all speculative. This error is very rare. You need to post as much info as possible.

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The wrclk is 320MHz and the rdclk is 32MHz. I am using Cyclone III. The reset is synchronized to the wrclk.

Is it 320MHz too high for dcfifo in Cyclone III? How could I find out the maximum frequency dcfifo supports?

Thanks,

Hua