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Altera_Forum
Honored Contributor
17 years agoMinimum Pulse Width (dcfifo)
Hi, I got many minimum pulse width timing violations (as the attached screenshot) related to the dcfifos in the design and don't know how to fix them. Could anyone point me to the right directi...
Altera_Forum
Honored Contributor
17 years agocheck your clks are not gated. If so register and make them global. Glitches on the clk signal cause this type of violation.