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Altera_Forum's avatar
Altera_Forum
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16 years ago

Minimum Pulse Width (dcfifo)

Hi, I got many minimum pulse width timing violations (as the attached screenshot) related to the dcfifos in the design and don't know how to fix them. Could anyone point me to the right directi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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check your clks are not gated. If so register and make them global. Glitches on the clk signal cause this type of violation.

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Hi Kaz,

Thank you for your reply. The clocks are all global. The attached are the clock report. Could anything else cause this?

Hua