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Altera_Forum
Honored Contributor
Honored ContributorMinimum Pulse Width (dcfifo)
Hi, I got many minimum pulse width timing violations (as the attached screenshot) related to the dcfifos in the design and don't know how to fix them. Could anyone point me to the right directi...
Altera_ForumHonored Contributor
Honored ContributorAmong other things: You need to check that your clk speed is not too high for fifos, that fifo reset is synchronised to faster clk. It is all speculative. This error is very rare. You need to post as much info as possible.
