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Honored Contributor
Honored ContributorMaximum output clock frequency
Hello,
I'm trying to build a random code generator using an Altera FPGA (since I do not have started yet, the choice of FPGA series is still open). To specify my system I need to know the maximum output frequency the FPGA can generate. Can anyone tell me where I can find information about the maximum IO frequency (which depends on the IO standard, I think)?? Thanks a lot!7 Replies
Altera_ForumHi RobertBochum,
You can find that information in the device datasheet, in Altera website. (https://www.altera.com/support/literature/lit-index.html)- Altera_Forum
Hi,
yes, I know where to find the literature concerning the devices. But since there are a lot of frequency specs within the datasheets I'm not really sure where to find information about the IO frequency. PLL frequency and core frequency as well as clock tree specs is easy to find but not the maximum IO frequency. Can you please give me further, i.e. more specific information where to find it? Thanks! - Altera_Forum
I will do my design and run it quartus for various devices and directly see what maximum output clock is possible. But be aware that fpga generated clocks suffer jitter
- Altera_Forum--- Quote Start --- Hi, yes, I know where to find the literature concerning the devices. But since there are a lot of frequency specs within the datasheets I'm not really sure where to find information about the IO frequency. PLL frequency and core frequency as well as clock tree specs is easy to find but not the maximum IO frequency. Can you please give me further, i.e. more specific information where to find it? Thanks! --- Quote End --- Hi, As I understand it, most of the Altera devices does not have the maximum IO frequency specs stated. As a workaround, it is recommended for you to perform IO model simulation ie with IBIS or Hspice to determine the maximum IO toggling frequency based on your board setup and IO setting.
- Altera_Forum
Hi,
Just to add on that you can download the IBIS and Hspice models from the following links: IBIS model - https://www.altera.com/support/support-resources/download/board-layout-test/ibis/ibs-ibis_index.html Hspice model - https://www.altera.com/support/support-resources/download/board-layout-test/hspice.html - Altera_Forum
Yes, I agreed with bfkstimchan's comment above. The toggle rate will base on the I/O performance target with specified maximum drive strength and load. The actual achievable I/O signal frequencies depends on design and system specific factors and is best determined using HSPICE/IBIS simulations.
There is a link published by Altera also recommend user to use IBIS/HSPICE to determine the I/O signal frequencies https://www.altera.com/support/support-resources/knowledge-base/solutions/rd01132009_577.html - Altera_Forum
Thanks a lot. I will try to simulate the io behaviour using IBIS models. Up to now, I never made such a simulation so it might take a while to get the right software etc.
