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Altera_Forum
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10 years ago

Maximum output clock frequency

Hello, I'm trying to build a random code generator using an Altera FPGA (since I do not have started yet, the choice of FPGA series is still open). To specify my system I need to know the max...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

I will do my design and run it quartus for various devices and directly see what maximum output clock is possible. But be aware that fpga generated clocks suffer jitter