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Altera_Forum
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10 years ago

Maximum output clock frequency

Hello, I'm trying to build a random code generator using an Altera FPGA (since I do not have started yet, the choice of FPGA series is still open). To specify my system I need to know the max...
Altera_Forum's avatar
Altera_Forum
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10 years ago

Yes, I agreed with bfkstimchan's comment above. The toggle rate will base on the I/O performance target with specified maximum drive strength and load. The actual achievable I/O signal frequencies depends on design and system specific factors and is best determined using HSPICE/IBIS simulations.

There is a link published by Altera also recommend user to use IBIS/HSPICE to determine the I/O signal frequencies

https://www.altera.com/support/support-resources/knowledge-base/solutions/rd01132009_577.html