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Altera_Forum
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11 years ago

Maximum output clock frequency

Hello, I'm trying to build a random code generator using an Altera FPGA (since I do not have started yet, the choice of FPGA series is still open). To specify my system I need to know the max...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Thanks a lot. I will try to simulate the io behaviour using IBIS models. Up to now, I never made such a simulation so it might take a while to get the right software etc.