Maximum Frequency Input on Cyclone 3 device

By Cyclone III specification, input toggle rates above 250 MHz are only supported for the LVDS standard. If you want to keep the specification strictly, an external LVDS driver could convert a single ended signal to LVDS. That's obviously more economic than using Arria or similar only to support 320 MHz single ended clock.

In any case, you'll have difficulties to find a driver supporting 320 MHz with a single ended standard. Single ended driven "LVDS", e.g. a low voltage signal from a clock oscillator should most likely work with Cyclone III.

If clock quality is critical, you'll get less jitter with an external LVDS repeater or differential output high speed comparator, that's not affected by the interfering signals present in a FPGA.

Ok,

Thanx for the reply. I'll do test and see the result.

In Cyclone 3 device data sheet :

.altera.com./literature./hb./cyc3./cyc3_ciii52001.pdf

P21 Cyclone III Devices LVDS Receiver Timing Specifications

They classify Max input clock frequency according to "Modes" *1, *2, *4, *7.....

What is a Mode ?

Is it a kind of protocol for LVDS transmittion ?

Thx

Remi

--- Quote Start ---

They classify Max input clock frequency according to "Modes" *1, *2, *4, *7.....

What is a Mode ? Is it a kind of protocol for LVDS transmittion ?

--- Quote End ---

modes is referring to serialization factor. Cyclone III SERDES uses software SERDES only, so you are not limited to the Modes provided by the altlvds MegaFunction.

LVDS implies no particular protocol, it's a synchronous raw binary data transmission.

Ok

Thanks for the reactivity !!

Cheers,

Remi