MAX10 Soft SERDES set_input_delay constraints

Hello,

I am planning on driving the MAX10 Soft SERDES input with a data rate of 720Mbps and a corresponding PLL reference input clock of 180MHz.  

I also plan on generating the serial data stream in the source FPGA device using DDR flip flops packed into IO blocks and treating the clock as a signal and generating the output clock by using DDR flip flops tied to logic '1' and '0' thereby guaranteeing that the tCO of both the serial data output and the tCO of the clock signal output are well matched with minimal skew.  I expect the skew to be no more than +/-150ps from the source device's data sheet.

I was constraining the MAX10 Soft SERDES data intput this way:

# Configured the soft serdes to run at 720Mbps input rate.

# 720/4 = 180MHz is the serdes input reference clock rate chosen

create_clock -name i_clk -period 5.555 [get_ports {i_clk}]

derive_pll_clocks

set_input_delay -clock i_clk -max 0.150 [get_ports {i_data}]

set_input_delay -clock i_clk -min -0.150 [get_ports {i_data}]

set_input_delay -clock i_clk -max 0.150 [get_ports {i_rst_l}]

set_input_delay -clock i_clk -min -0.150 [get_ports {i_rst_l}]

After timing analysis the tool reports in the Multi-Corner Timing Analysis Summary that the Worst Case Slack is as follows

Setup = -0.472, Hold = 0.195, Recovery = -2.610, and Removal = 1.149

What am I doing wrong that causes the negative Setup and Recovery slacks?