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sean793
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1 month ago
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MAX10 Soft SERDES set_input_delay constraints

Hello, I am planning on driving the MAX10 Soft SERDES input with a data rate of 720Mbps and a corresponding PLL reference input clock of 180MHz.   I also plan on generating the serial data stream i...
Programmable Logic Device
sean793's avatar
sean793
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1 month ago

After examining the Soft SERDES core parameters in the MegaWizard GUI I found that the PLL can phase shift the clock relationship between the input reference clock and the generated clock used to sample the data.  I set it to 45 degrees and recompiled and found that for the most part I meet timing.  See attached report.  However I don't meet the worst case slack for Recovery for pll clk[0].  Since Recovery Time applies only to asynchronously applied signals, does this mean that my reset input to the FPGA and hence to the PLL is failing timing?  Also, is this approach of manually adjusting the PLL phase shift until timing is met correct?  I would have thought this would be automatic by the Quartus Prime Standard Edition tool.