New ContributorMAX10 second PLL issue
Hello,
This is my configuration:
Device MAX10 (10M16DCF256C8G)
Quartus Prime Version 24.1std Build 1077
I need to use a second PLL, but it is not working. I have tried very hard and read the user manual several times. But without success.
Even with fairly relaxed values: 25 MHz inclk, 25 MHz outclk on the first PLL and 75 MHz on the second PLL.
1) Identical clock source: Both PLLs are controlled by the same pin (CLK0p, PIN_L3, can be used for PLL1 and PLL3).
-> Doesn't work. Only one PLL receives a “locked” signal (PLL1).
2) Cascading of PLLs: The first PLL outclk is connected to the second PLL inclk.
-> This does not work either.
3) Different clock sources: One PLL is controlled by PIN_L3 (CLK0p), the other by PIN_K6 (CLK1p). Both have 25 MHz, but different sources.
Unfortunately, I can only use these two pins at the moment.
-> Doesn't work either.
4) Adding CLKCTRL: I have tried adding CLKCTRL in many combinations, but without success.
I am frustrated because it won't work. What am I doing wrong?
Is there a limitation that I haven't recognized yet?
By the way: there is no hint or error message from Quartus.
I found the cause.
That was a good example of rubber duck debugging.
With the answers from @FvM and @ShengN_Intel in mind, I simplified the design until only the PLLs remained.
Now I noticed that PLL_3 never worked. And that was strange.
The cause was quickly found: in the hardware design, we forgot to connect the power supply for PLL_3 (VCCD_PLL3, PIN_D4).
How annoying! Fortunately, I can switch to PLL_2.
Thank you very much for your support. It was a great help.
Regards,
Helmut
