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New ContributorMAX10 second PLL issue
I found the cause.
That was a good example of rubber duck debugging.
With the answers from @FvM and @ShengN_Intel in mind, I simplified the design until only the PLLs remained.
Now I noticed that PLL_3 never worked. And that was strange.
The cause was quickly found: in the hardware design, we forgot to connect the power supply for PLL_3 (VCCD_PLL3, PIN_D4).
How annoying! Fortunately, I can switch to PLL_2.
Thank you very much for your support. It was a great help.
Regards,
Helmut
Super ContributorI had no problems yet to drive multiple PLLs of MAX10, Cyclone 10 LP and earlier FPGA series from a single clock input. Is it a ready-made evalboard or your own design? Can be that you have either an unstable clock source or a noisy PLL power supply.
Regards
Frank
- hemi
Thank you for your prompt reply! I am glad to hear that it should work in general.
I did not have this problem with Cyclone_V. But with MAX10.
It is our own design, which ran stably when using a PLL.
However, I will check the quality of the clock. Perhaps there is a problem here that has not been noticed until now.
Regards
Helmut
