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hemi's avatar
hemi
Icon for New Contributor rankNew Contributor
10 months ago
Solved

MAX10 second PLL issue

Hello, This is my configuration: Device MAX10 (10M16DCF256C8G) Quartus Prime Version 24.1std Build 1077 I need to use a second PLL, but it is not working. I have tried very hard and read the user...
  • hemi's avatar
    hemi
    10 months ago

    I found the cause.

    That was a good example of rubber duck debugging.

    With the answers from @FvM and @ShengN_Intel in mind, I simplified the design until only the PLLs remained.

    Now I noticed that PLL_3 never worked. And that was strange.

    The cause was quickly found: in the hardware design, we forgot to connect the power supply for PLL_3 (VCCD_PLL3, PIN_D4).

    How annoying! Fortunately, I can switch to PLL_2.

    Thank you very much for your support. It was a great help.

    Regards,

    Helmut

ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
10 months ago

Hi,


Please check this document page 31 https://cdrdv2-public.intel.com/666937/ug_m10_clkpll-683047-666937.pdf

Two PLLs are cascaded to each other through the clock network. If your design cascades PLLs, the source (upstream) PLL must have a low-bandwidth setting and the destination (downstream) PLL must have a high-bandwidth setting.


And page 53 for Programmable Bandwidth Parameter Settings.


Thanks,

Regards,

Sheng



hemi's avatar
hemi
Icon for New Contributor rankNew Contributor
10 months ago

Thank you for your prompt reply!
Yes, I saw that note. But I must admit that I didn't follow it consistently.
So, I'll try again.

Regards,
Helmut