New ContributorMAX10 FPGA design : some questions about clock and other aspects
Hi all,
finally I'm doing my first FPGA design (after tons with simpler CPLDs)
I'm targeting a MAX10 FPGA (10M08SCE144C8G is the exact part name).The design will be a kind of replacement installed on an old computer (mostly made with TTL logics).I have read the Intel® MAX® 10 guidelines and I want to feed the FPGA with a 6MHz clock signal coming from the old TTL hosting hardware.Should I simply connect this signal to one of the clock input of the MAX10 FPGA (for example pin 27 CLK0p like I did it in my schematics which I attach, it's missing the level shifters for proper 5V to 3.3VV translation though) or connect the signal to all 8 clock inputs CLK[3..0][p,n] so that they can drive all GCLK networks?Thanks in advance for any help or suggestion.
