Forum Discussion
Valerius
New Contributor
1 year agoMAX10 FPGA design : some questions about clock and other aspects
Hi all, finally I'm doing my first FPGA design (after tons with simpler CPLDs) I'm targeting a MAX10 FPGA (10M08SCE144C8G is the exact part name).The design will be a kind of replacement installed ...
sstrell
Super Contributor
1 year agoYou should only have to connect a single clock input but the user guide should help: https://www.intel.com/content/www/us/en/docs/programmable/683047/21-1/clocking-and-pll-overview.html