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Valerius's avatar
Valerius
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12 months ago

MAX10 FPGA design : some questions about clock and other aspects

Hi all, finally I'm doing my first FPGA design (after tons with simpler CPLDs) I'm targeting a MAX10 FPGA (10M08SCE144C8G is the exact part name).The design will be a kind of replacement installed ...
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RichardT_altera's avatar
RichardT_altera
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12 months ago

Hi,


You probably just need to connect the 6 MHz clock signal to one dedicated clock input pin rather than connecting it to all eight clock inputs to drive the global clock networks.

Let us know if you have further questions regarding this case.


Regards,

Richard Tan