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Altera_Forum's avatar
Altera_Forum
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11 years ago

MAX10 ADC & GPIO restrictions

I was combing through the hand book and found that using the ADC feature on the Max 10 parts dramatically cuts your available I/O, especially on the E144 package. In fact, and I was shocked by this, apparently you can only use 54% of the I/O on that package if you even turn on the ADC?

That seems a bit extreme, given that even if you use the dedicated analog in, you lose all of banks 1,2,8, and significant chunks of 3 and 7.

The question is why*, and is this a hard limit (imposed by Quartus) or just a "would cause noise in the ADC issue". Also, is this going to be fixed in the future, or is this a permanent "feature"?

Thanks!

* I assume it has to do with inducing noise on or near the SAR ADC.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Just tested with the eval kit (10M08 144pin part), and Quartus v14.0.2 does not enforce GPIO (non)placement in the areas mentioned.

    The Altera eval kit has bank8 populated with I/O for LEDs, DIP switch and user button which all work fine with ADC enabled. Not sure what the impact in ADC accuracy might be, if I get around to measuring this will update with my findings.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    I was told the ADC performance will degrade if violate the guideline. The reason this device is wirebond device and place the IO pin to close to the ADC pin will causing the SSN effect which will affect the ADC performance. Per my understanding, there is a critical warning appear after the compilation if there is any IO placement guideline violation. Better check the warning message before proceed :)

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Analog circuits are a quite sensitive to HF switching nearby due to SSN/crosstalk.

    I think it will be fine if you are using the nearby IO for asynchronous switching like reset.