matrix array in vhdl

Dear Tricky,

I understand what you said just before. I can't see the rows obtained in different clock cycles.

What Iam try to do is, I want the input matrix to be read row by row in different clock cycle. Then, the first row will be read out as output1 in column. It is possible I do like that? Thanks for reply.

delete the "matrix" signal insde the entity "test", and change the process to this:

process(clk)
begin
if rising_edge(clk) then
temp_row <= extract_row( input , to_integer(count) );
count <= count + 1;
end if;
end process;

Now, how can you expect to read anything "out". There is no output from test. Currently the rows are extracted into the temp_row signal

Dear Tricky,

I have fixed for the first problem. But Iam not clear the second problem. Can you explain more?

I expect the extracted rows to be read out by columns for the output. I hope you understand what I try to do. Thanks for reply.

first of all, your code has a compile error. Count needs to be initialised to "00" not "0". So you cant have simulated this exact code.

Secondly, because you have left my code pretty much intact, you're extracting the row from the internal signal matrix that is not connected to anything. You need to put "input", rather than "matrix" into the extract_row function.

Once I'd fixed these two problems, the row extraction works fine for me. Where do you expect the exctracted rows to go?

Dear Tricky,

I have simulate the code and the result shows that the 4x4 input matrix does not obtain in the correct clock cycle. All the rows obtain at the same clock cycle in one time. Below is the main code and testbench:

---main code

package newtype is

type row_t is array(0 to 3) of integer;

type matrix_t is array(0 to 3, 0 to 3) of integer;

end newtype;

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use work.newtype.all;

entity test is

port(input: in matrix_t;

clk: in std_logic);

end test;

architecture arch of test is

signal matrix : matrix_t;

signal temp_row : row_t;

signal count : unsigned(1 downto 0) := "0";

function extract_row( m : matrix_t; row : integer) return row_t is

variable ret : row_t;

begin

for i in row_t'range loop

ret(i) := m(row, i);

end loop;

return ret;

end function;

begin

process(clk)

begin

if rising_edge(clk) then

temp_row <= extract_row( matrix, to_integer(count) );

count <= count + 1;

end if;

end process;

end arch;

---testbench

library IEEE;

use IEEE.Std_logic_1164.all;

use IEEE.Numeric_Std.all;

use work.newtype.all;

entity test_tb is

end;

architecture bench of test_tb is

component test

port(input: in matrix_t;

clk: in std_logic);

end component;

signal input: matrix_t;

signal clk: std_logic;

constant clock_period: time := 10 ns;

signal stop_the_clock: boolean;

begin

uut: test port map ( input => input,

clk => clk );

stimulus: process

begin

input <= ((0,1,2,9), (3,5,6,10), (9,8,11,2), (9,7,1,6));

wait for 50ns;

stop_the_clock <= true;

wait;

end process;

clocking: process

begin

while not stop_the_clock loop

clk <= '1', '0' after clock_period / 2;

wait for clock_period;

end loop;

wait;

end process;

end;

What the mistake I have done? Help me please..thanks foR reply

Dear Tricky,

Did you mean like this:

package newtype is

type row_t is array(0 to 3) of integer;

type matrix_t is array(0 to 3, 0 to 3) of integer;

end newtype;

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use work.newtype.all;

entity test is

port(input: in matrix_t;

clk: in std_logic);

end test;

Thanks for reply

input : in integer range 0 to 3

is not an array at all, it is just a single value. to make an array and put it on a port you have to declare an array type in a package. If you you're going to use the row_t I declared for you , you need to move that into a package.

Dear Tricky,

Now I try to write for 2D matrix with integer data type. I change the std_logic_vector to integer as below:

--before:

entity TM is

port(input: in std_logic_vector (0 to 3);

clk: in std_logic);

end TM;

--after:

entity TM is

port(input: in integer range 0 to 3;

clk: in std_logic);

end TM;

It is right I declare my 2D input as code above? But, I think its 1D..Then I change to range (0 to 3, 0 to 3) but error occurs. What the right way should I write..Thanks for reply