Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

matrix array in vhdl

Dear all, I have 4x4 matrix and I want to read this matrix row by row on each clock cycle. For example, row1 is read in cycle1, row2 is read in cycle2 and so on. Can anyone give idea how to w...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Dear Tricky,

Did you mean like this:

package newtype is

type row_t is array(0 to 3) of integer;

type matrix_t is array(0 to 3, 0 to 3) of integer;

end newtype;

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use work.newtype.all;

entity test is

port(input: in matrix_t;

clk: in std_logic);

end test;

Thanks for reply