matrix array in vhdl

Dear Tricky,

Now I try to write for 2D matrix with integer data type. I change the std_logic_vector to integer as below:

--before:

entity TM is

port(input: in std_logic_vector (0 to 3);

clk: in std_logic);

end TM;

--after:

entity TM is

port(input: in integer range 0 to 3;

clk: in std_logic);

end TM;

It is right I declare my 2D input as code above? But, I think its 1D..Then I change to range (0 to 3, 0 to 3) but error occurs. What the right way should I write..Thanks for reply