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Altera_Forum
Honored Contributor
15 years agomatrix array in vhdl
Dear all, I have 4x4 matrix and I want to read this matrix row by row on each clock cycle. For example, row1 is read in cycle1, row2 is read in cycle2 and so on. Can anyone give idea how to w...
Altera_Forum
Honored Contributor
15 years agodelete the "matrix" signal insde the entity "test", and change the process to this:
process(clk)
begin
if rising_edge(clk) then
temp_row <= extract_row( input , to_integer(count) );
count <= count + 1;
end if;
end process;
Now, how can you expect to read anything "out". There is no output from test. Currently the rows are extracted into the temp_row signal