matrix array in vhdl

Dear Tricky,

I have simulate the code and the result shows that the 4x4 input matrix does not obtain in the correct clock cycle. All the rows obtain at the same clock cycle in one time. Below is the main code and testbench:

---main code

package newtype is

type row_t is array(0 to 3) of integer;

type matrix_t is array(0 to 3, 0 to 3) of integer;

end newtype;

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use work.newtype.all;

entity test is

port(input: in matrix_t;

clk: in std_logic);

end test;

architecture arch of test is

signal matrix : matrix_t;

signal temp_row : row_t;

signal count : unsigned(1 downto 0) := "0";

function extract_row( m : matrix_t; row : integer) return row_t is

variable ret : row_t;

begin

for i in row_t'range loop

ret(i) := m(row, i);

end loop;

return ret;

end function;

begin

process(clk)

begin

if rising_edge(clk) then

temp_row <= extract_row( matrix, to_integer(count) );

count <= count + 1;

end if;

end process;

end arch;

---testbench

library IEEE;

use IEEE.Std_logic_1164.all;

use IEEE.Numeric_Std.all;

use work.newtype.all;

entity test_tb is

end;

architecture bench of test_tb is

component test

port(input: in matrix_t;

clk: in std_logic);

end component;

signal input: matrix_t;

signal clk: std_logic;

constant clock_period: time := 10 ns;

signal stop_the_clock: boolean;

begin

uut: test port map ( input => input,

clk => clk );

stimulus: process

begin

input <= ((0,1,2,9), (3,5,6,10), (9,8,11,2), (9,7,1,6));

wait for 50ns;

stop_the_clock <= true;

wait;

end process;

clocking: process

begin

while not stop_the_clock loop

clk <= '1', '0' after clock_period / 2;

wait for clock_period;

end loop;

wait;

end process;

end;

What the mistake I have done? Help me please..thanks foR reply