Forum Discussion
Honored ContributorMarvell 88EE1111 PHY tranciever MDIO reg configuration
I'm trying to troubleshoot PHY for my dual Ethernet design on the DE2-115 Cyclone IV board. (I have to load my *.elf file twice for some reason for my design to work).
In trying to figure out what's I notice that the DE2-115 uses the Marvell 88EE1111 PHY Tranciever chip. As per IEEE 802.3 2015, MDIO registers 0-15 are standard, but 16-31 are manufacture dependent. Does anyone have any leads on configuring Marvell 88EE1111? The "datasheet" on their website is only a product brief and does not describe what the registers do. I noticed in an excerpt from the Altera University TSE example (below), register 20 is written to in order to set up delay for input/output clk, but neither Altera nor Marvell provide any further information on why they chose this value or what it means.// Write to register 20 of the PHY chip for Ethernet port 2 to set up delay for input/output clk
*(tse + 0xB4) = *(tse + 0xB4) | 0x0082;31 Replies
Altera_ForumA full copy of the Marvell datasheet comes on the DE2-115 CD, which can also be downloaded from Terasic's website.
Cheers, Alex- Altera_Forum
Thanks Alex. The document seems to be the same as their website and contains pin-out information (nothing about configuration registers). Some of their other products do, but some seem to be undocumented. I know that Reg 16 is for automatic crossover and Reg 20 is delay for the input/output clock.
- Altera_Forum
All,
As an update, I received an email from their sales team. It seems they only provide them with companies going into volume production: "Typically Marvell will only engage with customers that are building a product that will go into volume production. A NDA is required in order to get detailed data sheets. They do not engage with Universities or private individuals." - Altera_Forum
Indeed - my mistake. I found only the product brief shipped with the kit.
Going back to your original issue - does your code allow the Phy time to 'settle' before trying to configure it? By the time you re-load the elf it's been running for a number of seconds. Are you simply trying to do 'something' too early? Do you write to address 20 in your code? Comment it out if so. I doubt it's relevant. I remember not having to do any configuration to get the Phy working. Cheers, Alex - Altera_Forum
Hello Jsag,
I ran into a similar problem and I have working application with ethernet on the DE2-115 that i can share and some usefull info. Best Regards, Johi. - Altera_Forum
Johi, that would be great! I would appreciate. How would you send?
Best, Jsag - Altera_Forum--- Quote Start --- Indeed - my mistake. I found only the product brief shipped with the kit. Going back to your original issue - does your code allow the Phy time to 'settle' before trying to configure it? By the time you re-load the elf it's been running for a number of seconds. Are you simply trying to do 'something' too early? Do you write to address 20 in your code? Comment it out if so. I doubt it's relevant. I remember not having to do any configuration to get the Phy working. Cheers, Alex --- Quote End --- Alex, i'm not sure why, but it seems MDIO register 20 for setting up the delay for the I/O clock for Gigabit DDIO seems necessary in my case. I tried removing the line, but transmission seems to stop. Only when it is enabled does the traffic resume.
- Altera_Forum
Hello Jsag,
I think we could create a private channel to exchange the info you need, skype, mail, what is your proposition? I thought we could send private messages over the forum, but the admin has disabled mine, can you ? Best Regards, Johi. - Altera_Forum
I've found my Marvell datasheet. See the attached snippets of it that cover Address 20. There's also a timing diagram to show the impact of the bits being changed by your code. It seems to contradict my original statement about "not having to do any configuration to get the Phy working." Clearly a little too long ago for my grey matter to cope with...
Cheers, Alex - Altera_Forum
Alex,
Thanks! It seems the register is important of use with a DDIO for RX/TX delays. And for line loopbacks for testing. I thought it was for setting a delay value rather than binary on/off. I did find the reason for my needing to load twice. I wasn't configuring the PHY address within the Altera TSE MAC Megacore prior to configuring the Marvel 88EE1111 PHY (addresses 0x10 and 0x11 for DE2-115). Therefore, all my first-load configurations went to some imaginary PHY at default MDIO address 0x00. Since I was setting the correct MDIO PHY address at the end, the second-load configurations would be send to the correct address. Thus, I was require two loads of the *.elf file in order to get my design working. I simply set the PHY address first to fix the problem. Rookie mistake that took me two months to debug. (Johi, thank you as well!)
