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Altera_Forum
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9 years ago

Marvell 88EE1111 PHY tranciever MDIO reg configuration

I'm trying to troubleshoot PHY for my dual Ethernet design on the DE2-115 Cyclone IV board. (I have to load my *.elf file twice for some reason for my design to work). In trying to figure ou...
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Altera_Forum
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9 years ago

Alex,

Thanks! It seems the register is important of use with a DDIO for RX/TX delays. And for line loopbacks for testing. I thought it was for setting a delay value rather than binary on/off.

I did find the reason for my needing to load twice. I wasn't configuring the PHY address within the Altera TSE MAC Megacore prior to configuring the Marvel 88EE1111 PHY (addresses 0x10 and 0x11 for DE2-115). Therefore, all my first-load configurations went to some imaginary PHY at default MDIO address 0x00. Since I was setting the correct MDIO PHY address at the end, the second-load configurations would be send to the correct address. Thus, I was require two loads of the *.elf file in order to get my design working. I simply set the PHY address first to fix the problem. Rookie mistake that took me two months to debug.

(Johi, thank you as well!)