Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Marvell 88EE1111 PHY tranciever MDIO reg configuration

I'm trying to troubleshoot PHY for my dual Ethernet design on the DE2-115 Cyclone IV board. (I have to load my *.elf file twice for some reason for my design to work). In trying to figure ou...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Thanks Alex. The document seems to be the same as their website and contains pin-out information (nothing about configuration registers). Some of their other products do, but some seem to be undocumented. I know that Reg 16 is for automatic crossover and Reg 20 is delay for the input/output clock.