M9K utilization is different for the same RAM IP for two different projects.

I have a single-port Altera Avalon on-chip memory of 18,432 bytes with a data width of 32-bit instantiated in the two different QSYS subsystem used in different projects.

The first project consumes 18 M9K blocks for this memory IP as shown below. This seems correct since, each M9K has about 1 kB of memory, so 18kB of memory should consume about 18 M9K blocks.

Project 1 with lower RAM utilization

For, the same-IP the second project consumes 32 M9K blocks instead of 18 as shown in the image below:

Project 2 with higher RAM utilization

The settings for the RAM-IP are as shown in the image below:

RAM IP settings

Quartus Tool Version : Quartus 18.1 Standard

FPGA Device : MAX-10 10M50DAF256I7G

Please help us understand why the same RAM IPs have different utilization for different projects. Also, what settings can be made to the second project so that it consumes only 18 M9K blocks.

Thank you,

Akhilesh.