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Altera_Forum's avatar
Altera_Forum
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14 years ago

m25p26

Hi everybody,

I have finished a pcb design with a cyclone III Ep3c25q240, it is configurated in AS mode. There are two connector (10 pins), one for the JTAG and the other for the AS. When I download the .sof file into the FPGA (in JTAG mode with the JTAG connector and the usb blaster cable) there is no problem, but when I try to run the nios2 app it says it cannot reset the nios uP. Also, when I try to configure the flash (m25p16) with the .pof file there is no movement in te configuration progress bar in the quartus2 programmer (in AS mode with the AS connector and the usb blaster cable).

Any help?

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  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    The problem in the clock seems fixed, there was a short circuit between the case of the oscillator and one of his path. Now I have tried to configure the flash and the fpga with the jic file, but without success. I think something is wrong in the AS interface. I also have run succesfully the source&probe test with a switch and one led.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    i also would start with a simpler design. the Sources and Probes function can be useful during board bring up

    you could try to configure the AS device using JTAG with a .jic file
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I have seen that instead of a clean external clk of 50 MHz, I have a clk of 1KHz. I'm confused because the circuit apparently seems correct. I attach the schematic, If anyone can help I would be grateful. Thanks.

    Also the AS interface doesn`t work.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    It could be a good idea to check the signals on the flash with an oscilloscope to see if there is any hardware problem. You can also configure the FPGA with an SFL image and try to access the flash through the JTAG connector.

    As for your Nios design, there could be a number of reasons, such as timing problems on your FPGA project, bad clock input, or processor kept into reset (be careful with the reset signal, the reset_n port created by SOPC builder is active low, not high).

    You could try to do a simpler design first, with no CPU and just a flashing led as an example, to check that the FPGA and its clock source are working properly.