Forum Discussion

MK_ABQ's avatar
MK_ABQ
Icon for Contributor rankContributor
2 years ago
Solved

LVDS

Hi, I am using Intel Arria 10 GX FPGA development kit. DK-DEV-10AX115S-A The development kit has two FMC connectors FMC A and FMC B. There are LVDS standard pins in the connector. I am trying t...
Configuration
Generic Io
Other Ips
  • FvM's avatar
    FvM
    2 years ago

    You don't need to connect differential termination to see specified LVDS voltage range. Unterminated pins simply swing to VCCIO and GND for 1 and 0 state. In so far termination isn't required to see LVDS output working. There must be another elementary problem in your test, e.g. probing wrong FMC pins.

_AK6DN_'s avatar
_AK6DN_
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

LVDS (low voltage differential signaling) is normally implemented as a current source/sink between the P and N driver.

So you need a (typical) 100ohm differential load at the receiver, and measure the voltage across that.

So put 100ohms between your P and N outputs and measure the differential voltage across that as you drive a '1' and '0' internally.

Measuring the unloaded driver pins is not generally meaningful as no current can flow thru an effective infinite load resistance.

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago

You don't need to connect differential termination to see specified LVDS voltage range. Unterminated pins simply swing to VCCIO and GND for 1 and 0 state. In so far termination isn't required to see LVDS output working. There must be another elementary problem in your test, e.g. probing wrong FMC pins.