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MK_ABQ
Contributor
ContributorLVDS
Hi, I am using Intel Arria 10 GX FPGA development kit. DK-DEV-10AX115S-A The development kit has two FMC connectors FMC A and FMC B. There are LVDS standard pins in the connector. I am trying t...
You don't need to connect differential termination to see specified LVDS voltage range. Unterminated pins simply swing to VCCIO and GND for 1 and 0 state. In so far termination isn't required to see LVDS output working. There must be another elementary problem in your test, e.g. probing wrong FMC pins.
FvM
Super Contributor
Super ContributorHi,
your setup isn't clear. If you chose LVDS IO standard, a pin pair is used. So how do you measure three pins? There 6 pins involved with 3 LVDS outputs.
your setup isn't clear. If you chose LVDS IO standard, a pin pair is used. So how do you measure three pins? There 6 pins involved with 3 LVDS outputs.
