Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorLVDS signal in 1.5V bank
Hi,
I am using arria II GX FPGA with DDR3. To map the DDR3 signals whose IO standard is SSTL 1.5, I am giving the supply VCCIO as 1.5V. Now, I want to use the LVDS clock for this bank. Can I give LVDS clock to this bank, as in the datasheet, it is written that LVDS signals are powered by VCCPD? Thanks in advance4 Replies
Altera_Forumthanks a lot.....
i got my doubt cleared as it is written in handbook that OCT function for RECEIVE is available only in Arria II GZ devices while my device is Arria II GX, so I shall have to terminate them near FPGA- Altera_Forum
You might take a look at the Arria II device handbook, Volume 1 Chapter 6 (I/O Features) to see how to terminate SSTL signals.
I haven't looked at the reference board you're referring to, but assuming there is are series resistors near the FPGA on the address lines, you should be able to remove those resistors and use the series OCT of the Arria. Just make sure to add Rup and Rdn resistors if you want to use OCT with calibration. - Altera_Forum
Hey...thanks for the answer.....
Now, I am having another doubt. As I am interfacing DDR3 with ARRIA II, I took reference of PCIe kit from Altera. In that schematic, they are doing SSTL termination for Address lines near DDR3 as address lines have no "on chip termination" function, while the data lines are terminated near FPGA. Now I want to know whether we could remove those termination resistors near Altera and use OCT function of FPGA. If it is possible, then I can not understand the reason for external termination. - Altera_Forum
Yes, if you use a dedicated clock input you can receive an LVDS clock, even though the bank VCCIO is 1.5V. You could confirm this by adding the signals in Pin Planner with the appropriate I/O standards, etc. Just make sure to supply VCCPD with 2.5V. Also depending on the input you might need external termination for the LVDS input.
