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Altera_Forum
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15 years ago

LVDS signal in 1.5V bank

Hi, I am using arria II GX FPGA with DDR3. To map the DDR3 signals whose IO standard is SSTL 1.5, I am giving the supply VCCIO as 1.5V. Now, I want to use the LVDS clock for this bank. Can I give ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

You might take a look at the Arria II device handbook, Volume 1 Chapter 6 (I/O Features) to see how to terminate SSTL signals.

I haven't looked at the reference board you're referring to, but assuming there is are series resistors near the FPGA on the address lines, you should be able to remove those resistors and use the series OCT of the Arria. Just make sure to add Rup and Rdn resistors if you want to use OCT with calibration.