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Altera_Forum
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15 years ago

LVDS signal in 1.5V bank

Hi, I am using arria II GX FPGA with DDR3. To map the DDR3 signals whose IO standard is SSTL 1.5, I am giving the supply VCCIO as 1.5V. Now, I want to use the LVDS clock for this bank. Can I give ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Yes, if you use a dedicated clock input you can receive an LVDS clock, even though the bank VCCIO is 1.5V. You could confirm this by adding the signals in Pin Planner with the appropriate I/O standards, etc. Just make sure to supply VCCPD with 2.5V. Also depending on the input you might need external termination for the LVDS input.