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Honored Contributor
Honored ContributorLVDS signal in 1.5V bank
Hi, I am using arria II GX FPGA with DDR3. To map the DDR3 signals whose IO standard is SSTL 1.5, I am giving the supply VCCIO as 1.5V. Now, I want to use the LVDS clock for this bank. Can I give ...
Altera_ForumHonored Contributor
Honored Contributorthanks a lot.....
i got my doubt cleared as it is written in handbook that OCT function for RECEIVE is available only in Arria II GZ devices while my device is Arria II GX, so I shall have to terminate them near FPGA
