Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

LVDS signal in 1.5V bank

Hi, I am using arria II GX FPGA with DDR3. To map the DDR3 signals whose IO standard is SSTL 1.5, I am giving the supply VCCIO as 1.5V. Now, I want to use the LVDS clock for this bank. Can I give ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hey...thanks for the answer.....

Now, I am having another doubt. As I am interfacing DDR3 with ARRIA II, I took reference of PCIe kit from Altera. In that schematic, they are doing SSTL termination for Address lines near DDR3 as address lines have no "on chip termination" function, while the data lines are terminated near FPGA. Now I want to know whether we could remove those termination resistors near Altera and use OCT function of FPGA. If it is possible, then I can not understand the reason for external termination.