New ContributorLVDS SERDES Transmitter / Receiver IP
Hello,
I am trying to design a VHDL program with the ALTLVDS_RX and ALTLVDS_TX IPs. I can't find any example on your site, and the clocking system with the fractional PLL is giving me problems. I would need to cascade the PLLs but I want to use the internal PLL for each IP.
Do you have any solution to propose me on the design of the clock signal between the 2 IP ?
I looked at all the documentation I found on your site on this subject ( LVDS SERDES TRANSMITTER / RECEIVER , Handbook)
Thanking you in advance !!!!
Antoine
Hi,
Couple of things:
1) The ALTLVDS IP does not support single-ended I/O standard. So, the rx_in and tx_out pins should be assigned I/O standard as LVDS.
2) Next, when you assign it as LVDS, you need to insert an ALTIOBUF in differential mode for each of the IP.
Regards
