Forum Discussion
New ContributorLVDS SERDES Transmitter / Receiver IP
Hello,
I am trying to design a VHDL program with the ALTLVDS_RX and ALTLVDS_TX IPs. I can't find any example on your site, and the clocking system with the fractional PLL is giving me problems. I would need to cascade the PLLs but I want to use the internal PLL for each IP.
Do you have any solution to propose me on the design of the clock signal between the 2 IP ?
I looked at all the documentation I found on your site on this subject ( LVDS SERDES TRANSMITTER / RECEIVER , Handbook)
Thanking you in advance !!!!
Antoine
Hi,
Couple of things:
1) The ALTLVDS IP does not support single-ended I/O standard. So, the rx_in and tx_out pins should be assigned I/O standard as LVDS.
2) Next, when you assign it as LVDS, you need to insert an ALTIOBUF in differential mode for each of the IP.
Regards
6 Replies
Ash_R_AlteraRegular Contributor
Hi,
May I know which FPGA device family are you planning to target.
Regards
CHARLES_AntoineHi,
I use the FPGA cyclone V GX.
Regards
- Ash_R_Altera
Hi,
I am not sure of the type of application you are looing for. You may wan to check on the Intel design store. Design Store for Intel® FPGAs
In case you want to debug the issues that you are facing in your custom design, you may want to look into knowledge database. Go to Knowledge Data Base Search (intel.com) and search for ALTLVDS.
We can also help you with any specific error or issue you may be facing.
Regards.
- CHARLES_Antoine
hi I have this problem on quartus and i don't find a solution for my system. I can send you my Quartus project.
- CHARLES_Antoine
I would just like to start by making these two IPs proposed by quartus work
- Ash_R_Altera
Hi,
Couple of things:
1) The ALTLVDS IP does not support single-ended I/O standard. So, the rx_in and tx_out pins should be assigned I/O standard as LVDS.
2) Next, when you assign it as LVDS, you need to insert an ALTIOBUF in differential mode for each of the IP.
Regards
