Forum Discussion

CHARLES_Antoine's avatar
CHARLES_Antoine
Icon for New Contributor rankNew Contributor
5 years ago
Solved

LVDS SERDES Transmitter / Receiver IP

Hello, I am trying to design a VHDL program with the ALTLVDS_RX and ALTLVDS_TX IPs. I can't find any example on your site, and the clocking system with the fractional PLL is giving me problems. I ...
  • Ash_R_Altera's avatar
    Ash_R_Altera
    5 years ago

    Hi,

    Couple of things:

    1) The ALTLVDS IP does not support single-ended I/O standard. So, the rx_in and tx_out pins should be assigned I/O standard as LVDS.

    2) Next, when you assign it as LVDS, you need to insert an ALTIOBUF in differential mode for each of the IP.

    Regards


Ash_R_Altera's avatar
Ash_R_Altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

I am not sure of the type of application you are looing for. You may wan to check on the Intel design store. Design Store for Intel® FPGAs

In case you want to debug the issues that you are facing in your custom design, you may want to look into knowledge database. Go to Knowledge Data Base Search (intel.com) and search for ALTLVDS.

We can also help you with any specific error or issue you may be facing.


Regards.