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CHARLES_Antoine's avatar
CHARLES_Antoine
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4 years ago
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LVDS SERDES Transmitter / Receiver IP

Hello, I am trying to design a VHDL program with the ALTLVDS_RX and ALTLVDS_TX IPs. I can't find any example on your site, and the clocking system with the fractional PLL is giving me problems. I ...
  • Ash_R_Intel's avatar
    Ash_R_Intel
    4 years ago

    Hi,

    Couple of things:

    1) The ALTLVDS IP does not support single-ended I/O standard. So, the rx_in and tx_out pins should be assigned I/O standard as LVDS.

    2) Next, when you assign it as LVDS, you need to insert an ALTIOBUF in differential mode for each of the IP.

    Regards


CHARLES_Antoine's avatar
CHARLES_Antoine
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4 years ago

hi I have this problem on quartus and i don't find a solution for my system. I can send you my Quartus project.