I have wrote this code for implementing a neural network.What it does is to take some values(inputs) and some weights and computes the SUM(values*weigths).What i want to do is to check if the total sum(values*weights)< threshold and correct the weights in order to sum(values*weights)>=threshold.I think that i have to store the weights on a look up table and change the values in order to sum(values*weights)>=threshold.How i can do this?.My code is : LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_SIGNED.ALL; ENTITY ANN IS GENERIC ( m : INTEGER := 4; -- Number of inputs or weights b : INTEGER := 8); --Number of bits per input or weight PORT ( x1,x2,x3,x4: IN UNSIGNED(b-1 DOWNTO 0); w : IN UNSIGNED(b-1 DOWNTO 0); clk: IN STD_LOGIC; y : buffer UNSIGNED(2*b-1 DOWNTO 0); id : buffer bit); END ANN; ARCHITECTURE NEURAL OF ANN IS TYPE weights IS ARRAY (1 TO m) OF UNSIGNED(b-1 DOWNTO 0); TYPE inputs IS ARRAY (1 TO m) OF UNSIGNED(b-1 DOWNTO 0); BEGIN PROCESS(clk,w,x1,x2,x3,x4) VARIABLE weight : weights; VARIABLE input : inputs; VARIABLE prod,acc : UNSIGNED(2*b-1 DOWNTO 0); VARIABLE sub : UNSIGNED(2*b-1 DOWNTO 0); BEGIN IF (clk'EVENT AND CLK='1') THEN weight:=w&weight(1 TO m-1); END IF; input(1):=x1; input(2):=x2; input(3):=x3; input(4):=x4; acc:=(OTHERS=>'0'); FOR j IN 1 TO m LOOP prod:=input(j)*weight(j); acc:=acc+prod; END LOOP; y<=acc; END IF; END PROCESS; END NEURAL;

I notice a couple of problems with the code first: --- Quote Start --- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_SIGNED.ALL; --- Quote End --- You cannot use signed and unsigned libraries the same file, only one or the other. if you need both, then replace arith/unsigned/signed with ieee.numeric_std.all instead. --- Quote Start --- PROCESS(clk,w,x1,x2,x3,x4) VARIABLE weight : weights; VARIABLE input : inputs; VARIABLE prod,acc : UNSIGNED(2*b-1 DOWNTO 0); VARIABLE sub : UNSIGNED(2*b-1 DOWNTO 0); BEGIN --- Quote End --- Why are you storing these as variables and not signals? Do you understand the differences between the 2 and how they both behave? It may simulate correctly but unless you are carefull the synthesiser may just do something you weren't expecting. You have to be more careful with variables and synthesis. --- Quote Start --- END IF; input(1):=x1; input(2):=x2; input(3):=x3; input(4):=x4; acc:=(OTHERS=>'0'); FOR j IN 1 TO m LOOP prod:=input(j)*weight(j); acc:=acc+prod; END LOOP; y<=acc; END IF; END PROCESS; END NEURAL; --- Quote End --- Again, I dont think you want to loop and have and accumulate like this. In your code, it will try and add up m values in 1 clock cycle, the more values there are, the slower your FMAX can be. For your actual question, you havent said how you need to change the weights if the sum is > theshold. Is there some formula for this (good), or do you have to work it out on an iterative basis (bad). There are many ways to store values in memories. You can instantiate an altsyncram or infer the ram from code. Until you explain how you intend to do such things, I dont think we can explain further.

Looking again at your code: the stored value weight(m) is never used. you expect to multiply and accumulate unregistered values. At most, I recon the max clock speed will be very slow, maybe a 2Mhz if you are lucky!

I store those as variables because every time i insert an input their values will be changed.As far as i know variables are used inside process(because their values change every clock time) and signals are constant values.(if i am right).I will try to explain you what exactly i want to do so you can help me. I want to insert some inputs(lets say 3),each of one has one weight(random).So i would like to multiply each input with its own weight and then compute the sum of them.Then i would like to compare this sum with a predetermined threshold and if the sum that i have computed is greated than this threshold its ok.But if the sum is less than the threshold i would like to correct the values of the weights so the total sum is greater than the threshold.I hope i explained it good. P.S Sorry for my bad english

--- Quote Start --- I store those as variables because every time i insert an input their values will be changed.As far as i know variables are used inside process(because their values change every clock time) and signals are constant values.(if i am right).I will try to explain you what exactly i want to do so you can help me. --- Quote End --- this is incorrect. Variables can exist in any process, function or procedure. A signal exists inside an architecture. The difference is that variables are updated immediatly, whereas signals are updated at the next delta. This can have a huge effect on the code you are writing. Take a look at the following code: signal a, b, c : std_logic; process(clk) variable x, y, z : std_logic; begin if rising_edge(clk) x := input; y := x; z := y; output <= z; a <= input; b <= a; c <= b; output <= c; end if; end process; The version using variables desicribes a 1 register delay from input to output. The version using signals describes a 4 register delay from input to output. This is because the variables are updated imediatly, they pass the value straight through. Because the signals are all updated at the same time, they are all updated at the clock edge, therefore each one is a register. now, just to screw with your head, here is a version of the a/b/c method above, but using variables, that describes exactly the same behaviour. process(clk) variable a,b,c : std_logic; begin if rising_edge(clk) output := c; c := b; b := a; a := input; end if; end process; Now, because variables before the previous one updates, this will produce a pipeline of 4 registers as well. The trick to learning VHDL is not learning the language, but first understanding the hardware you are trying to discribe. Only then can you use tricks of the language to help you discribe things above. No offence, but it looks and sound like you are trying to write VHDL like a programming language, which it is not - it is a hardware description language. --- Quote Start --- I want to insert some inputs(lets say 3),each of one has one weight(random).So i would like to multiply each input with its own weight and then compute the sum of them.Then i would like to compare this sum with a predetermined threshold and if the sum that i have computed is greated than this threshold its ok.But if the sum is less than the threshold i would like to correct the values of the weights so the total sum is greater than the threshold.I hope i explained it good. P.S Sorry for my bad english --- Quote End --- And again, this points to you thinking VHDL is a programming language. FPGAs and hardware are very good at doing static things and doing repetative tasks. They are not good at decision making. What you want to do sounds like a very complicated task for an FPGA to do.

Thanks for your quick response(again).You are right that i think most like vhdl is a programming language because i am a newbie in vhdl.But from the things you wrote you mean that what i want to do is difficult?The first step as far as i know is a simple MAC unit.The difficult part is the part that i have to adjust the weights in order for sum>threshold.Can you please tell me at least if the first part(the MAC unit) is correct?As i mentioned above i want to insert 3 inputs,each of one has a weight and then multiply each input with each weight and finally sum.Thanks again.

LUT help!!! | Altera Community

70 Replies

Altera_Forum
Honored Contributor
16 years ago
Ok i will try to change variables to signals and i will check if the results are ok.
Altera_Forum
Honored Contributor
16 years ago
--- Quote Start ---
I think that the more important difference between variables and signals is that variables can only be put into process and that variables are being updated immediately.Thats why i used variables in my code wherever i considered them as necessary.
--- Quote End ---

This is why you need to go and learn VHDL and digital design.

Variables can go in any process, function or procedure. Shared variables can even go in the architecture like signals (but you can forget about those until you have learned VHDL properly!) and are updated immediatly.

The fact they update immediatly is of no importance for what you are doing. it has been recommended time and time again that you use signals. They behave more like real hardware, and you keep talking about more efficient implementation. First stop - forget about variables completly. YOU DO NOT NEED THEM!
Altera_Forum
Honored Contributor
16 years ago
I think that the more important difference between variables and signals is that variables can only be put into process and that variables are being updated immediately.Thats why i used variables in my code wherever i considered them as necessary.
Altera_Forum
Honored Contributor
16 years ago
--- Quote Start ---
Not true. variables are created once (at elaboration time, not each time the process is triggered), and then updated over and over like anything else. Its all about where you place the variables in the code that makes the difference. for example (inside a clocked process):

a := input
output <= a;

connects a wire between input and output. output is a register

output<= a;
a := input;

puts a register between the input and the output. a and output are registers. If the variable didnt store the values between clocks (as you suggest) then the output would be unconnected all the time. if you do the same thing with signals:

a <= input;
output <= a;

is exactly the same as:

output <= a;
a <= input;

(they both place a register between input and output)

This is why you have to be seriously careful with variables, because unlike signals, the procedural placement is very important.
--- Quote End ---

i added some bolded comments for clarity. i understand that you are trying to explain variables, but "connects a wire between input and output" seemed confusing and i wanted to clear things up.
Altera_Forum
Honored Contributor
16 years ago
My personal opinion about preserved variables: They are rather bad coding style, because the primary purpose of variables is different, but they work obviously. Altera is using them by the way in the Quartus VHDL templates counter example.

Triggerman's storage problem has been finally clarified. I think, it's no necessary to spoonfeed more detailed examples of RAM versus regsister storage. It's more effective to evaluate the basic options and their limitations by making Quartus compile some test code. As said, the test designs must have output signals (that actually depend on stored data somehow), otherwise the results are void.
Altera_Forum
Honored Contributor
16 years ago
Gah! I really neet to refresh my VHDL. :(
Altera_Forum
Honored Contributor
16 years ago
Theres a difference between getting advice and someone doing the work for you:

My advice : learn digital logic if you want to code it yourself. If you want us to do it for you, then pay someone (I charge $50/hour)
Altera_Forum
Honored Contributor
16 years ago
Thats why i want your advise because you are an fpga specialist.I want to make my code more efficient in order to expand it for future work in which i will may want to use a bigger image.For example an 60x60 image may wont even work with this kind of code because of the big use of resources.Thank you
Altera_Forum
Honored Contributor
16 years ago
--- Quote Start ---
This was an example that's why i don't declare an output.As far the result of this code is correct.And the count statement also works.Do you have any suggestion on how to do this(what i described in the previous post)?
--- Quote End ---

What you wrote will work.

rbugalho is very correct though when it comes to resource usage. your code would map to ALOT of memories with alot of wasted memory (ie memory you can no longer access AT ALL). This is the problem when you dont understand the underlying hardware - it becomes very inneficient and very wasteful!
Altera_Forum
Honored Contributor
16 years ago
--- Quote Start ---

Ignoring that elephant in the room, your code doesn't make sense anyway.
VHDL "variables" are, let's say, temporary things: they are created each time a "process" is triggered.
Which means, for exameple, that "count" will always be "1" -- the "count := count + 1" statement will not carry on to the next clock cycle.

--- Quote End ---

Not true. variables are created once (at elaboration time, not each time the process is triggered), and then updated over and over like anything else. Its all about where you place the variables in the code that makes the difference. for example (inside a clocked process):

a := input
output <= a;

connects a wire between input and output

output<= a;
a := input;

puts a register between the input and the output. If the variable didnt store the values between clocks (as you suggest) then the output would be unconnected all the time. if you do the same thing with signals:

a <= input;
output <= a;

is exactly the same as:

output <= a;
a <= input;

(they both place a register between input and output)

This is why you have to be seriously careful with variables, because unlike signals, the procedural placement is very important.

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LUT help!!!

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