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I think that the more important difference between variables and signals is that variables can only be put into process and that variables are being updated immediately.Thats why i used variables in my code wherever i considered them as necessary.
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This is why you need to go and learn VHDL and digital design.
Variables can go in any process, function or procedure. Shared variables can even go in the architecture like signals (but you can forget about those until you have learned VHDL properly!) and are updated immediatly.
The fact they update immediatly is of no importance for what you are doing. it has been recommended time and time again that you use signals. They behave more like real hardware, and you keep talking about more efficient implementation. First stop - forget about variables completly. YOU DO NOT NEED THEM!
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