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Ignoring that elephant in the room, your code doesn't make sense anyway.
VHDL "variables" are, let's say, temporary things: they are created each time a "process" is triggered.
Which means, for exameple, that "count" will always be "1" -- the "count := count + 1" statement will not carry on to the next clock cycle.
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Not true. variables are created once (at elaboration time, not each time the process is triggered), and then updated over and over like anything else. Its all about where you place the variables in the code that makes the difference. for example (inside a clocked process):
a := input
output <= a;
connects a wire between input and output
output<= a;
a := input;
puts a register between the input and the output. If the variable didnt store the values between clocks (as you suggest) then the output would be unconnected all the time. if you do the same thing with signals:
a <= input;
output <= a;
is exactly the same as:
output <= a;
a <= input;
(they both place a register between input and output)
This is why you have to be seriously careful with variables, because unlike signals, the procedural placement is very important.
Honored Contributor
