I have wrote this code for implementing a neural network.What it does is to take some values(inputs) and some weights and computes the SUM(values*weigths).What i want to do is to check if the total sum(values*weights)< threshold and correct the weights in order to sum(values*weights)>=threshold.I think that i have to store the weights on a look up table and change the values in order to sum(values*weights)>=threshold.How i can do this?.My code is : LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_SIGNED.ALL; ENTITY ANN IS GENERIC ( m : INTEGER := 4; -- Number of inputs or weights b : INTEGER := 8); --Number of bits per input or weight PORT ( x1,x2,x3,x4: IN UNSIGNED(b-1 DOWNTO 0); w : IN UNSIGNED(b-1 DOWNTO 0); clk: IN STD_LOGIC; y : buffer UNSIGNED(2*b-1 DOWNTO 0); id : buffer bit); END ANN; ARCHITECTURE NEURAL OF ANN IS TYPE weights IS ARRAY (1 TO m) OF UNSIGNED(b-1 DOWNTO 0); TYPE inputs IS ARRAY (1 TO m) OF UNSIGNED(b-1 DOWNTO 0); BEGIN PROCESS(clk,w,x1,x2,x3,x4) VARIABLE weight : weights; VARIABLE input : inputs; VARIABLE prod,acc : UNSIGNED(2*b-1 DOWNTO 0); VARIABLE sub : UNSIGNED(2*b-1 DOWNTO 0); BEGIN IF (clk'EVENT AND CLK='1') THEN weight:=w&weight(1 TO m-1); END IF; input(1):=x1; input(2):=x2; input(3):=x3; input(4):=x4; acc:=(OTHERS=>'0'); FOR j IN 1 TO m LOOP prod:=input(j)*weight(j); acc:=acc+prod; END LOOP; y<=acc; END IF; END PROCESS; END NEURAL;

I notice a couple of problems with the code first: --- Quote Start --- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_SIGNED.ALL; --- Quote End --- You cannot use signed and unsigned libraries the same file, only one or the other. if you need both, then replace arith/unsigned/signed with ieee.numeric_std.all instead. --- Quote Start --- PROCESS(clk,w,x1,x2,x3,x4) VARIABLE weight : weights; VARIABLE input : inputs; VARIABLE prod,acc : UNSIGNED(2*b-1 DOWNTO 0); VARIABLE sub : UNSIGNED(2*b-1 DOWNTO 0); BEGIN --- Quote End --- Why are you storing these as variables and not signals? Do you understand the differences between the 2 and how they both behave? It may simulate correctly but unless you are carefull the synthesiser may just do something you weren't expecting. You have to be more careful with variables and synthesis. --- Quote Start --- END IF; input(1):=x1; input(2):=x2; input(3):=x3; input(4):=x4; acc:=(OTHERS=>'0'); FOR j IN 1 TO m LOOP prod:=input(j)*weight(j); acc:=acc+prod; END LOOP; y<=acc; END IF; END PROCESS; END NEURAL; --- Quote End --- Again, I dont think you want to loop and have and accumulate like this. In your code, it will try and add up m values in 1 clock cycle, the more values there are, the slower your FMAX can be. For your actual question, you havent said how you need to change the weights if the sum is > theshold. Is there some formula for this (good), or do you have to work it out on an iterative basis (bad). There are many ways to store values in memories. You can instantiate an altsyncram or infer the ram from code. Until you explain how you intend to do such things, I dont think we can explain further.

Looking again at your code: the stored value weight(m) is never used. you expect to multiply and accumulate unregistered values. At most, I recon the max clock speed will be very slow, maybe a 2Mhz if you are lucky!

I store those as variables because every time i insert an input their values will be changed.As far as i know variables are used inside process(because their values change every clock time) and signals are constant values.(if i am right).I will try to explain you what exactly i want to do so you can help me. I want to insert some inputs(lets say 3),each of one has one weight(random).So i would like to multiply each input with its own weight and then compute the sum of them.Then i would like to compare this sum with a predetermined threshold and if the sum that i have computed is greated than this threshold its ok.But if the sum is less than the threshold i would like to correct the values of the weights so the total sum is greater than the threshold.I hope i explained it good. P.S Sorry for my bad english

--- Quote Start --- I store those as variables because every time i insert an input their values will be changed.As far as i know variables are used inside process(because their values change every clock time) and signals are constant values.(if i am right).I will try to explain you what exactly i want to do so you can help me. --- Quote End --- this is incorrect. Variables can exist in any process, function or procedure. A signal exists inside an architecture. The difference is that variables are updated immediatly, whereas signals are updated at the next delta. This can have a huge effect on the code you are writing. Take a look at the following code: signal a, b, c : std_logic; process(clk) variable x, y, z : std_logic; begin if rising_edge(clk) x := input; y := x; z := y; output <= z; a <= input; b <= a; c <= b; output <= c; end if; end process; The version using variables desicribes a 1 register delay from input to output. The version using signals describes a 4 register delay from input to output. This is because the variables are updated imediatly, they pass the value straight through. Because the signals are all updated at the same time, they are all updated at the clock edge, therefore each one is a register. now, just to screw with your head, here is a version of the a/b/c method above, but using variables, that describes exactly the same behaviour. process(clk) variable a,b,c : std_logic; begin if rising_edge(clk) output := c; c := b; b := a; a := input; end if; end process; Now, because variables before the previous one updates, this will produce a pipeline of 4 registers as well. The trick to learning VHDL is not learning the language, but first understanding the hardware you are trying to discribe. Only then can you use tricks of the language to help you discribe things above. No offence, but it looks and sound like you are trying to write VHDL like a programming language, which it is not - it is a hardware description language. --- Quote Start --- I want to insert some inputs(lets say 3),each of one has one weight(random).So i would like to multiply each input with its own weight and then compute the sum of them.Then i would like to compare this sum with a predetermined threshold and if the sum that i have computed is greated than this threshold its ok.But if the sum is less than the threshold i would like to correct the values of the weights so the total sum is greater than the threshold.I hope i explained it good. P.S Sorry for my bad english --- Quote End --- And again, this points to you thinking VHDL is a programming language. FPGAs and hardware are very good at doing static things and doing repetative tasks. They are not good at decision making. What you want to do sounds like a very complicated task for an FPGA to do.

Thanks for your quick response(again).You are right that i think most like vhdl is a programming language because i am a newbie in vhdl.But from the things you wrote you mean that what i want to do is difficult?The first step as far as i know is a simple MAC unit.The difficult part is the part that i have to adjust the weights in order for sum>threshold.Can you please tell me at least if the first part(the MAC unit) is correct?As i mentioned above i want to insert 3 inputs,each of one has a weight and then multiply each input with each weight and finally sum.Thanks again.

LUT help!!! | Altera Community

70 Replies

Altera_Forum
Honored Contributor
16 years ago
This was an example that's why i don't declare an output.As far the result of this code is correct.And the count statement also works.Do you have any suggestion on how to do this(what i described in the previous post)?
Altera_Forum
Honored Contributor
16 years ago
That code is going to map to... nothing.
Your module doesn't even have an output, so it will be reduced to absolutely nothing.

Ignoring that elephant in the room, your code doesn't make sense anyway.
VHDL "variables" are, let's say, temporary things: they are created each time a "process" is triggered.
Which means, for exameple, that "count" will always be "1" -- the "count := count + 1" statement will not carry on to the next clock cycle.

Ignoring that second elephant in the room, your code makes 16 assignments in a given clock cycle.
If that were to be mapped to memory blocks, it would mean 16 16x8 memory blocks.
At the very least, 8 16x8 memory blocks, since the M4K/M9K blocks are dual ported.

Damn, you need a good book on VHDL and digital electronics.
Altera_Forum
Honored Contributor
16 years ago
Here is an example code of inserting an 16x16 image.In every clock cycle i read the first 16 values,then other 16 etc.
--suppose we want to insert an 16x16 image.Each element is an integer 0 to 255
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY input IS

PORT( x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16 : IN INTEGER RANGE 0 TO 255;
clk,load : IN STD_LOGIC);

END input;

ARCHITECTURE behavioral OF input IS

TYPE row IS ARRAY(1 TO 16) OF INTEGER RANGE 0 TO 255;

BEGIN

PROCESS(clk)

VARIABLE row1,row2,row3,row4,row5,row6,row7,row8,row9,row10,row11,row12,row13,row14,row15,row16 : row;--it could be done with the use of signal as well
VARIABLE count : INTEGER:=(1);

BEGIN

IF(clk'EVENT AND clk='1') THEN
IF(load='1') THEN
IF(count<17) THEN
row1(count):=x1;
row2(count):=x2;
row3(count):=x3;
row4(count):=x4;
row5(count):=x5;
row6(count):=x6;
row7(count):=x7;
row8(count):=x8;
row9(count):=x9;
row10(count):=x10;
row11(count):=x11;
row12(count):=x12;
row13(count):=x13;
row14(count):=x14;
row15(count):=x15;
row16(count):=x16;

count:=count+1;
END IF;
END IF;
END IF;

END PROCESS;

END behavioral;

There is a need for the values to be stored,because in specific clock cycles i want add/substract some values so i must have them somewhere stored.
Altera_Forum
Honored Contributor
16 years ago
A LUT is a look up table. input values are translated into other values, so effectivly it is a ROM.
Altera_Forum
Honored Contributor
16 years ago
An array in a HDL code can have different meanings:
- it can describe a collection of individual register bits. The bits can be accesses individually without restrictions, but the "wiring" consumes a lot of FPGA resources

- it can describe FPGA internal RAM, if the requirements for RAM inference are met. Internal RAM can have maximal two ports, so only two register entities can be accessed simultaneously. In some cases, multiple "array" elements can be arranged as one RAM word, limited of course by the available RAM word width respectively the total amount of RAM.

Unfortunately, you didn't yet give a clear example of intended array usage, so it's difficult to decide about a possible solution. In the last code example you posted (on page three of this thread) the array is neither supplied with individual data nor needs to store it.
Altera_Forum
Honored Contributor
16 years ago
Ok i will try to explain you what i have done in order to understand and see if i can do something in my case.I want to insert an 20x20 image.The values of the image are the same type(integer) so i decide to insert it as an 20x20 array.The way i follow to do this is to declare 20 one dimensional arrays which would be the rows of the array.So i only need 20 inputs(each of them for one row).So i need 20 clock cycles to insert the entire image.What i did is to insert every clock cycle one value for each input and full the rows.For example in the first clock i will now the first element for each of the rows,in the second clock the second element of each row etc.I test it and works great.Am i doing something wrong?Is there any more efficient way to do this?Thanks
Altera_Forum
Honored Contributor
16 years ago
Creating a component to do the operation won't save resources by itself -- the component will just be instantiated as many times as you need.

However, in many designs, arithmetic operations aren't required to produce a result every clock and the arithmetic logic can be "shared" among multiple needs.

To do this, you need to draw a dependency diagram with the operations you need and then try to schedule them in order to reduce the number of add/sub that are performed in each clock cycle.
Altera_Forum
Honored Contributor
16 years ago
Another question i would like to ask is this : Say that i use add/substraction of 4 elements too many times in my code.It would be more efficient to make a component that does this add/substraction so i can save of alus?Thank you very much.
Altera_Forum
Honored Contributor
16 years ago
Beware of arrays in HDL, though.
VHDL/Verilog allow you to use arrays in ways that can't actually be implemented in hardware or that would take too many logic resources to do so.

You need to understand what resources you actually have and how to "map" your problem to them.

In practice, you probably want to have them mapped over to the synchronous RAM blocks.
This can be achieved either by using (properly) arrays, or by explicitly using RAM/ROM primitives.
Altera_Forum
Honored Contributor
16 years ago
Thanks for your quick response.My question maybe was stupid,but i want to briefly describe the behavior of a look up table.I was not looking for the definition of the word.From the answer you mentioned i suppose i was right about the use of arrays as look up tables.Thanks again

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LUT help!!!

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