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Altera_Forum's avatar
Altera_Forum
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15 years ago

LUT help!!!

I have wrote this code for implementing a neural network.What it does is to take some values(inputs) and some weights and computes the SUM(values*weigths).What i want to do is to check if the total s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

An array in a HDL code can have different meanings:

- it can describe a collection of individual register bits. The bits can be accesses individually without restrictions, but the "wiring" consumes a lot of FPGA resources

- it can describe FPGA internal RAM, if the requirements for RAM inference are met. Internal RAM can have maximal two ports, so only two register entities can be accessed simultaneously. In some cases, multiple "array" elements can be arranged as one RAM word, limited of course by the available RAM word width respectively the total amount of RAM.

Unfortunately, you didn't yet give a clear example of intended array usage, so it's difficult to decide about a possible solution. In the last code example you posted (on page three of this thread) the array is neither supplied with individual data nor needs to store it.