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Altera_Forum
Honored Contributor
Honored ContributorLUT help!!!
I have wrote this code for implementing a neural network.What it does is to take some values(inputs) and some weights and computes the SUM(values*weigths).What i want to do is to check if the total s...
Altera_ForumHonored Contributor
Honored ContributorThat code is going to map to... nothing.
Your module doesn't even have an output, so it will be reduced to absolutely nothing. Ignoring that elephant in the room, your code doesn't make sense anyway. VHDL "variables" are, let's say, temporary things: they are created each time a "process" is triggered. Which means, for exameple, that "count" will always be "1" -- the "count := count + 1" statement will not carry on to the next clock cycle. Ignoring that second elephant in the room, your code makes 16 assignments in a given clock cycle. If that were to be mapped to memory blocks, it would mean 16 16x8 memory blocks. At the very least, 8 16x8 memory blocks, since the M4K/M9K blocks are dual ported. Damn, you need a good book on VHDL and digital electronics.
